| 摘要 |
PURPOSE:To obtain an integrated circuit form of CRC generator with low power consumption even applied to a digital television system by applying parallel processing to a signal to attain low speed processing and use of a CMOS. CONSTITUTION:An 8-bit parallel signal from a terminal 1 and an 8-bit parallel output signal from a shift register 7 are applied to an input of a half adder circuit 2. The output of the half adder circuit 2 is given to matrix circuits 3, 4, where addition is conducted. The output of the shift register 7 is led to a parallel output terminal 8 and also branched and given as one input to the half adder circuit 2. Moreover, since the period of the clock signal has only to be operated by 4 times subcarrier, a CMOS circuit is used and the power consumption is reduced. |
