发明名称 SYNTHESIZER SYSTEM RADIO RECEIVER
摘要 PURPOSE:To set the frequency dividing ratio of a programmable frequency divider accurately with simple circuit by providing a memory means which reads and stores a count value by using the 1st counter means when a memory set pulse is received and applies the result to the programmable frequency divider as the frequency dividing ratio. CONSTITUTION:When an analog output of an analog signal generator 22 is set a maximum value in the initial state and an oscillating frequency fv of a variable frequency oscillator 23 is the highest, a signal processing circuit 24 is brought into the operation stand-by state and fed to other input terminal of an AND circuit 33, then a memory set pulse MS is outputted from an exclusive OR circuit 34. When the memory set pulse MS is outputted in this way, the memory means 35 reads the count value of the 1st counter means 17 as the frequency dividing ratio N and stores it and set the frequency dividing ratio of the frequency divider 11 by applying it to the programmable frequency divider 11.
申请公布号 JPS60172829(A) 申请公布日期 1985.09.06
申请号 JP19840028871 申请日期 1984.02.17
申请人 SHARP KK 发明人 KOBAYASHI SADAO
分类号 H04B1/26 主分类号 H04B1/26
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