发明名称 MULTIPLEX SYSTEM
摘要 PURPOSE:To increase the transmission speed of a picture signal by using a coding device operated with a clock frequency independently of a clock frequency of a transmission line and providing a terminal device output data detecting circuit. CONSTITUTION:When a clock (c) is outputted in a clock frequency ft(1Mb/s- 1.544 Mb/s) from an adaptive bit allocation multiplexer 1 to a buffer memory circuit 3 storing a picture coded data to a transmitter 2 operated in a clock frequency f1(1Mb/s-1.544 Mb/s) independently of a clock frequency f1(f1=1.544 Mb/s) of a transmission line (a), the buffer memory circuit 3 transmits a picture oded data (b) having the same transmission speed as the clock frequency ft. The clock frequency ft depends on the storage capacity of the buffer memory circuit 3 storing the picture coding data. In an example of this execution, the storage capacity of the buffer memory circuit 3 of the transmitter 2 is selected as 1Mb/s-1.544 Mb/s.
申请公布号 JPS60172852(A) 申请公布日期 1985.09.06
申请号 JP19840028053 申请日期 1984.02.17
申请人 NIPPON DENKI KK 发明人 SHIBUYA TOORU;NISHIWAKI MITSUO
分类号 H04J3/04;H04J3/16;H04N1/00 主分类号 H04J3/04
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