发明名称 MEMORY MODULE AND MANUFACTURING SYSTEM
摘要 PURPOSE:To shorten access time of a memory module by making an output control signal execute a write command of data of plural UV-EPROMs instead of an element selection signal. CONSTITUTION:Plural UV-EPROMM0-M3 are selected by an element selection signal of a decoder X1, and data writing is executed. When the writing is terminated properly, a program input terminal anti PGM and a supply terminal VPP of the ROMM0-M3 which are unnecessary for reading out by wiring modification are pulled up. Simultaneously, a chip select terminal anti CS of the ROM M0-M3 are commonly connected. At the time of reading out, the ROMM0-M3 are simultaneously selected, the decoder X1 sequentially acts in correspondence to an output control signal CE', and output control signals outputted from terminal antis Y1-Y3 are impressed to an output control terminal anti OE. Reading is executed by the output control signal outputted from the decoder X1 without delay and access time of a memory module is shortened compared with the case where wiring modification is not conducted. Moreover, its generation can be facilitated because of only wiring modification.
申请公布号 JPS60171698(A) 申请公布日期 1985.09.05
申请号 JP19840026814 申请日期 1984.02.15
申请人 TOSHIBA KK 发明人 KAGEYAMA SEIICHI
分类号 G06F12/06;G11C16/02;G11C17/00;H01L21/8246;H01L21/8247;H01L27/10;H01L27/112;H01L29/788;H01L29/792 主分类号 G06F12/06
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