| 摘要 |
<p>A memory access control apparatus comprises an address queueing circuit (CAQ) for storing a real address at which image data can be stored, a correspondence storing circuit (CAT) for storing a correspondence between a real address and a logical address, and a control circuit (IMC) for controlling a writing operation in such a way that, at a real address taken from the address queueing circuit, a next transfer unit of data is written, after the transfer unit of data previously stored at that real address has been read, by specifying the corresponding logical address, whereby a continuous reading can be effected without stopping due to a writing operation.</p> |
