| 摘要 |
<p>A memory matrix array (12) consists of a plurality of memory cells (11) with addresses expressed by a plurality of bits. The parity bit for the data stored in all of the memory cells of each linear memory cell array in the row direction are stored in the corresponding one of a plurality of parity storage cells (14A). Storage is made into second and third parity storage cells (14B, 14C), respectively, the parity bits for the data stored in all of the memory cells which are specified such that the corresponding bits of the addresses of said memory cells are high in logical level. In a read mode, the parity is read out from said first to third parity storage cells (14A, 14B, 14C) of the parity memory circuit (13).</p> |
