| 摘要 |
Driving circuit 5 of power FET 1, having intrinsic capacitance 2 between gate and source, receives from control circuit 4 a first (A) and a second (B) pulse voltage, said voltages being shifted 180 DEG out of phase each from other and having a fixed frequency and a duty cycle ratio which varies up to a maximum of 50%.
<??>The pulse voltage are applied to the ends of the primary winding of transformer 50 which therefore results supplied by alternately positive and negative pulses.
<??>Some diodes (51A, 51B and 52A 52B) rectify the voltage on the secondary windings of the transformer and render available on nodes R, S a control pulse voltage having a frequency twice of that one of the pulses in input to the transformer and duty cycle ratio which varies up to a maximum of 100%.
<??>The control pulse voltage, when it rises to logical/electrical level 1, charges very fast intrinsic capacitance 2 of FET 1 because bipolar transisor 57 is nearly immediately switched OFF.
<??>On the contrary, when the control pulse voltage falls to logical/electrical level 0, bipolar transistor 57 is switched ON by the same charge voltage of intrinsic capacitance 2 and allow a fast discharging of such capacitance.
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