| 摘要 |
PURPOSE:To eliminate the influence of power source noises by providing a capacitor between the source and gate of a PMOS transistor constituting an inverter together with an NMOS transistor and a parallel circuit of a capacitor and resistance between the drain and gate of the PMOS transistor. CONSTITUTION:An inverter circuit is constituted by respectively connecting the drain and gate of a PMOS transistor (TR) 6 to the drain and gate of an NMOS TR7 and sources of the TRs 6 and 7 to a power supply terminal and earthing potential. A capacitor 5 is connected between the source and gate of the TR6 and another capacitor 8 is connected between the gate and drain of the TR6. An equivalent high resistance composed of NMOS TRs 10 and 11, whose gates are connected with each other, is connected in parallel with the capacitor 8. Moreover, the TRs 10 and 11 are connected in such a way that PN junction formed between the source and well electrode and drain and well electrode have a relation of forward bias and reverse bias to each other. In such a way inverted phase voltages of power source noises are generated and influences of noises can be eliminated.
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