发明名称 DEBUG SUPPORTING SYSTEM
摘要 PURPOSE:To confirm sufficiently the working state of a central controller and to grasp the cause of debug easily by collecting the internal state information of the central controller by a debug adder and transmitting the collected information to a debug processor. CONSTITUTION:A command for collecting the internal state of the central controller CC when the central controller CC is shifted from its operating state to stop state is transmitted from the debug processor DBG to the debug adder ADP. The debug adder ADP monitors the working state of the central controller CC through a part of a parallel receiving signal line PR. When detecting the shift of the central controller CC from its operating state to the stop state, the debug adder ADP forms a command to collect the internal information of the central controller CC, and after accumulating the command in a register REG, transmits the command to the central processor CC to collect the internal information of the central controller CC and transmit the collected information to the debug processor DBG.
申请公布号 JPS60169950(A) 申请公布日期 1985.09.03
申请号 JP19840025771 申请日期 1984.02.14
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 INOUE SABUROU;TSUBOI JIROU;SHIMOKIBA SHIYUUICHI;ICHIKAWA MASATAKA
分类号 G06F11/28;G06F11/36 主分类号 G06F11/28
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