| 摘要 |
PURPOSE:To obtain a chattering preventing circuit without any delay to response by inhibiting an input to other circuit for a prescribed time with one detection output of a leading detecting circuit or a trailing detection circuit. CONSTITUTION:An input signal via a 3-wave circuit 2 for noise elimination enters latch circuits 5, 6 through AND gates 3, 4. Since latch circuits 5, 6 are reset, the latch circuit 5 is set at the leading point of time and the latch circuit 6 is set at the trailing point of time (because of presence of an inverter). When either of both the latch circuits 5, 6 is set, an output (Q') closes either of the AND gates 3, 4 so as to inhibit the input to the other latch circuit. Moreover, an output of one latch circuit is an output (g) via OR gates 8, 12 and also the operation of a counter 11 is started so as to count clocks from a terminal 10. When the clocks are counted for a prescribed value, the AND gates 3, 4 are opened by resetting both the latch circuits 5, 6 so as to release the inhibition. |
