发明名称 INSTRUCTION CONTROL SYSTEM
摘要 PURPOSE:To reduce disorder of a pipeline and shorten the branch instruction execution time by writing preliminarily the analysis result of a branch instruction in an associative memory when the branch instruction is first executed in a data processor of the pipeline control system. CONSTITUTION:At a branch instruction execution time, the address of the branch instruction, an instruction word in the branch destination, and the analysis result are stored in an associative memory 24 of an instruction control unit 2 by signals 241, 215, and 211 respectively. The address (signal 241) of the branch instruction is used as a retrieval input to read out contents of the associative memory 24 when the same branch instruction is executed hereafter, and thereby, disorder of the pipeline processing between the branch instruction and the instruction in the branch destination is reduced, and the branch instruction execution time is shortened.
申请公布号 JPS60168238(A) 申请公布日期 1985.08.31
申请号 JP19840021794 申请日期 1984.02.10
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 NISHIMUKAI TADAHIKO;HASEGAWA ATSUSHI;UCHIYAMA KUNIO;TAKAMOTO YOSHIFUMI
分类号 G06F9/38 主分类号 G06F9/38
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