| 摘要 |
PURPOSE:To make real-time data rate conversion possible by selecting two data obtained by sampling input data, which is sampled with a P[Hz] clock, with a Q[Hz] clock. CONSTITUTION:Input data of 160[nsec] data rate is sampled by registers 3a and 3b and is sampled by registers 3c and 3d. Meanwhile, the P[Hz] clock has the wave tail and the wave front differentiated with the Q[Hz] clock by a wave tail differentiating circuit 5 and a wave front differentiating circuit 6 to obtain set and reset signals of a set/reset circuit 7. The output of the set/reset circuit 7 is used as a selecting signal of outputs of registers 3c and 3d in a selector 9, and thereby, outputs of registers 3c and 3d are so delayed that the edge of the output of the set/reset circuit 7 does not overlap undefined parts of registers 3c and 3d. By this constitution, real-time conversion is possible.
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