发明名称 MULTIPLIER CHECK SYSTEM
摘要 PURPOSE:To simplify circuit constitution by comparing the value, which is obtained by multiplying a multiplied value and an all ''0'' detection result, with the value of the total sum of residues to check the operation of a multiplier. CONSTITUTION:A residue is obtained in a residue operating circuit RES5 with respect to the output of a recorder RCD; and meanwhile, a residue of a multiplicand due to a residue operating circuit RES1 is obtained, and residues are multiplied by a multiplier MLT2. If a multiplier is all ''0'', it is detected, and multiplication is performed again by a multiplier MLT3, and the result is inputted to a terminal EOR-3 of a comparator EOR. The residue of a residue sum adder ADR is inputted to one terminal EOR-2 and is compared to check the operation of the multiplier. All ''0'' of the multiplier is detected by a detector DET, and residue multiplication is performed by the multiplier MLT3, and a resultant residue is obtained.
申请公布号 JPS60168235(A) 申请公布日期 1985.08.31
申请号 JP19840024135 申请日期 1984.02.10
申请人 FUJITSU KK 发明人 MIYANAGA HIDEO
分类号 G06F7/38;G06F7/499;G06F7/52;G06F7/533;G06F11/00;G06F11/16 主分类号 G06F7/38
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