发明名称 |
LOW POWER CMOS INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To reduce or prevent the through currents in a back-up mode by setting the threshold voltage VTN of an n-MOSTR at a high level and the threshold voltage VTP of a p-MOSTR at a low level respectively only in the back-up mode. CONSTITUTION:A CMOS inverter shown in the diagram is driven by a power supply 1 in a normal mode, and VTN-VTP<¦V1¦ is satisfied between the voltage V1 and threshold voltages VTP and VTN of MOSTRs 3 and 4. In this case, the static characteristics of the inverter are equal to those of a conventional type. When the power supply 1 is not applicable, a current is supplied automatically from a power supply 2. The voltage V2 of the power supply 2 is set lower than the voltage V1 to satisfy VTN-VTP>¦V2¦. Thus the TR3 conducts only when 0<=V1n<=V2-¦VTP¦ is satisfied: while the TR4 conducts only when VTN <=V1n<V2 is satisfied. Therefore both TRs 3 and 4 are not conductive when V2-¦VTP¦<V1n<VTN is satisfied. Thus no through current flows. |
申请公布号 |
JPS60167523(A) |
申请公布日期 |
1985.08.30 |
申请号 |
JP19840021696 |
申请日期 |
1984.02.10 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
HORIGUCHI SHINJI;SHIMOHIGASHI KATSUHIRO;AOKI MASAKAZU;NAKAGOME YOSHINOBU;IKENAGA SHINICHI |
分类号 |
H03K19/0948;G11C11/407;G11C11/408;H03K17/16;H03K17/687;H03K19/00;H03K19/094;H03K19/0952 |
主分类号 |
H03K19/0948 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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