| 摘要 |
PURPOSE:To avoid prevention of high integration of a semiconductor storage by enabling taking a transistor layout pitch for a word line driving with regard to a semiconductor storage holding a dynamic random access memory by a word line pitch and making such pitches affect one another. CONSTITUTION:Low decoders 16 and 17 are arranged on both ends of a word line direction in a memory cell array 11. A word line drive circuit (for example, composed of transistors 18 and 19) and word line clamp circuit (for example, composed of transistor 20 or 22) are arranged on the side in the vicinity of a low decoder with respect to a word line WL. A reset circuit (for example, composed of a transistor 40) is arranged on the side away from the low decoder. When said clamp circuit or a low system reset clock signal phiR is at a high level, which is a non-selective condition, while the corresponding word line is reset, the storage clamps the word to a ground level. |
