发明名称 INSULATED GATE TYPE FIELD-EFFECT TRANSISTOR
摘要 PURPOSE:To obtain a MOS type field-effect transistor having small input capacitance and ON resistance and the high effective utilization efficiency of a chip by forming a high concentration layer to the surface of a drain region between channel substrates and shaping a floating electrode not connected to a power supply to the high concentration layer. CONSTITUTION:A distance (w) between channel substrates 3 extends over several hundred mum - 1,000mum in chip size of 5mmX5mm and at the rating of forward currents of 10A, and a donor layer 10 having the same high concentration as source regions 4 is shaped into a drain region 2 between the substrates 3. The high- concentration donor layer 10 is separated from each P-type channel substrate by approximately 30mum in order to maintain the withstanding voltage of the rating of 500V in the surface of a drain. Gate electrodes 5 coat the drain regions in which there is no P-type channel substrate and high-concentration donor layer. A source electrode 7 is opposed to a drain electrode 8. A floating electrode 11 not connected to a power supply by a metal such as Al is shaped onto the surface of the high-concentration donor layer. Accordingly, the electrode having extremely low resistivity such as an Al electrode is applied to the surface of the high-concentration drain, thus reducing spreading resistance in the lateral direction to a negligible small value.
申请公布号 JPS61159767(A) 申请公布日期 1986.07.19
申请号 JP19850000208 申请日期 1985.01.07
申请人 HITACHI LTD 发明人 ONO KIKUO;SHIMIZU YOSHITERU;NAGANO TAKAHIRO;NAITO MASAMI;OKAMURA MASAHIRO
分类号 H01L29/08;H01L29/41;H01L29/78 主分类号 H01L29/08
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