发明名称 PRIORITY SELECTION SYSTEM
摘要 PURPOSE:To use the resource of a system effectively by providing a means which alters the selection algorithm of a shared circuit when the 1st shared circuit is in use, and selecting a request to use the 2nd shared circuit speedily. CONSTITUTION:A bus arbiter checks on contention among all requests to use according to normal selection logic in the beginning and returns a shared bus use permit signal OK0 when a communication controller has top priority. The communication controller which receives the use permit signal OK0 sends a command (a) to an address bus A. The bus arbiter once receiving the signal (a) from a buffer register 1 operates a command detecting circuit 3 to detect a priority selection logic altering command CHG, and holds a receiver number REN in a register 2 and also outputs a priority selection logic alteration enable signal to a register 2. A priority selecting circuit 4 receives the priority selection logic alteration enable signal to alter the priority logic of a common bus request on the basis of information of the register 2, and changes a use request corresponding to the device number indicated in the register 2 into the top priority level.
申请公布号 JPS60167055(A) 申请公布日期 1985.08.30
申请号 JP19840021667 申请日期 1984.02.10
申请人 HITACHI SEISAKUSHO KK 发明人 IWAMOTO YOSHIHARU
分类号 G06F9/48;G06F13/362;G06F13/364 主分类号 G06F9/48
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