发明名称 LINE SEQUENCE DECIDING CIRCUIT
摘要 PURPOSE:To always generate a line sequence switching signal at a correct switching phase by setting a switching timing of a switching circuit by an applicable pulse signal selected by the switching circuit, an output signal produced by comparing an SECAM system chroma signal voltage with a reference voltage, and a pulse signal whose frequency is sufficiently lower than scan line frequency. CONSTITUTION:The value of a capacity 10 is so set that a charging time required for the level of a decision output (g) reaches a reference voltage E0 from the fall lowest limit level Emin is longer than a pulse width of a vertical synchronizing signal l and is shorter than its period. In the course of the decision output (g) rising up to the rise highest limit level Emax, even if the level fluctuation occurs to a comparison output (h) due to the leak current of the capacity 10, this level fluctuation is no longer added to an FF13 because an AND gate 15 is not supplied with the vertical synchronizing signal l. Therefore the FF13 makes no inverse operation erroneously and its output (j) is retained at a low level L as it is, thereby maintaining a selective output (f) in correct switching phase and thus causing no malfunction.
申请公布号 JPS60167588(A) 申请公布日期 1985.08.30
申请号 JP19840021673 申请日期 1984.02.10
申请人 HITACHI SEISAKUSHO KK 发明人 UEKI YUKIYA;AKITAKE ISAO;MATSUMOTO SHIYUUZOU
分类号 H04N9/465;H04N9/47 主分类号 H04N9/465
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