| 摘要 |
<p>PURPOSE:To decrease the rising time of the clock signal, etc., on a signal line and to perform high-speed operation by inputting a signal to the signal line of the driver part of a driver built-in type active matrix substrate at plural positions. CONSTITUTION:Clock signal input terminals 301 and 302 are provided to another-side terminals of clock signal lines of data-side drivers 115 and 116. Further, clock signal input termimals 303 and 304 are provided to another-side terminals of clock signal lines of data-side driver 113 and 114 and clock signals are inputted to both terminals of the clock signal lines. Consequently, the signal lines are shortened in length to half and widened in width by twice; the time constant of the signal lines is 75nsec and the time when the clock signal rises up to 90% of a source voltage is 170nsec. Therefore, the drivers are operates at 1MHz.</p> |
