| 摘要 |
PURPOSE:To simplify the device constitution and to save amount of laying wires by providing a information transfer control line for specific call and a couple of information transfer control line between a processor at logical high-orer and a processor at logical low-order. CONSTITUTION:The processor incorporated in a control section 14 is at logical high-order in general and a processor incorporated in a coding/decoding section 11 is at logical low-order, then the control information signal via a bus line from a control section 14 to the coding/decoding section 11 is transferred with priority over other processor. An information transfer control signal 118 displaying the will of information transfer is transmitted to the coding/decoding section 11 as the 1st step. The conding/decoding section 11 receives the information transfer control signal 118 returns an information transfer control signal 119 representing the display of will of the reception of an information signal to the control section 14. The information transfer control signals 118, 119 in this case are transmitted/received via a couple of information transfer control lines.
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