发明名称 DATA PROCESSOR
摘要 PURPOSE:To obtain an output data having a property close to that of an original signal by calculating data before and after a low reliability data and discriminating a level between the result of calculation and a prescribed value so as to attain alternately the round-off and cutoff of the result of calculation alternatively thereby generating a new data. CONSTITUTION:Suppose that a data A is a data (1101(2)) corresponding to analog + increment + 5 and a data C is a data (1010(2)) corresponding to +2. When the data A is inputted to a latch circuit 2 and the data C is outputted from a latch circuit 4, an output of a full adder circuit 16 is 10111(2). Since the data (MSB) of the most significant bit is logical ''1'', an output of an inverter 18 is logical 0 and the carry-in is logical 0 and no addition is conducted at all. In taking out a data of the high-order 4-bit of the output of the full adder circuit 16, it corresponds to 1 bit shift and an average value interpolation data (1011(2)) between the data A and C is obtained and the data (LSB) of the least significant bit of the output of the full adder circuit 16 is cut off in this case. That is, the average value interpolation data is +3.5(2+5)/2 from the analogical point of view, while the actual interpolation data is +3.
申请公布号 JPS60165135(A) 申请公布日期 1985.08.28
申请号 JP19840021087 申请日期 1984.02.08
申请人 CANON KK 发明人 KOUZUKI SUSUMU;TAKEI MASAHIRO;MASUI TOSHIYUKI;HIRASAWA KATAHIDE;KASHIDA MOTOICHI
分类号 H04B14/04 主分类号 H04B14/04
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