发明名称 DATA PROCESSOR
摘要 PURPOSE:To obtain an output data having a property close to that of an original signal by operating a data before and after a low reliability data and attaining alternatively the alternate round-off and cutoff in the same rate for the result of calculation at each generation of the low reliability data so as to generate a new data. CONSTITUTION:An output of a latch circuit 14 is shown in Fig. (b) and when the level is logical 1, an output data of a latch circuit 2 is a low reliability data. When an input of a full adder circuit 16 is 1011(2)(+3) and 0110(2)(-2), the output of the full adder circuit is 10001(2) when the carry-in is logical 0 and 10010(2) when the output is logical 1. Thus, the data fed to a data selector 8 is respectively 1000(2)(0) and 1001(2)(+1). If a fraction is produced when two inputs are calculated to the full adder circuit 16, that is, when the least significant bit (LSB) of the output data of the full adder circuit 16 is logical 1, the full adder circuit 16 acts like an average value arithmetic circuit rounding off the fraction by the carry-in or acts like an average value arithmetic circuit cutting off the fraction. Then the replaced interpolated data is alternately the rounded-off data just before and after and the cut-off data alternately.
申请公布号 JPS60165136(A) 申请公布日期 1985.08.28
申请号 JP19840021088 申请日期 1984.02.08
申请人 CANON KK 发明人 TAKEI MASAHIRO;KOUZUKI SUSUMU;MASUI TOSHIYUKI;HIRASAWA KATAHIDE;KASHIDA MOTOICHI
分类号 H04B14/04 主分类号 H04B14/04
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