| 摘要 |
PURPOSE:To decrease number of elements and occupied area by precharging an inverse amplifying section during a period when a logical section is precharged in the inverting amplifying section receiving an output of the logical section so as to attain high speed and stable operation. CONSTITUTION:When a level of a clock signal phi is logical H, a logical input sampling is applied, a logical output level appears at a node 1 and it is inverted and appears at a node 2 being an output terminal of the inverse amplifier section 20. When the clock signal phi is logical L, a P-channel transistor MP applies precharging and a P-channel transistor (TR) M1 is turned off. Since other P- channel TRM2 is conducted during time t2-t2 and an N-channel TRM3 is nonconductive, the node 2 is precharged regardless of a signal. Thus, all nodes are precharged, malfunction due to charge suring is prevented to allow high speed and stable operation. |
