| 摘要 |
PURPOSE:To attain high speed operation and stability by providing the 1st inverter circuit connected between an output of an NAND circuit and one input of an NOR circuit and the 2nd inverter circuit connected between an output of the NOR circuit and other input of the NAND circuit to decrease a through-current without excess timewise delay. CONSTITUTION:When an output data signal D changes from 0 level to 1 level, an output OL of the NOR circuit 8 changes from 1 level to 0 level, its inverted output OL' changes from 0 level to 1 level, and an output OH of the NAND circuit 7 changes from 1 level to 0 level by receiving the output OL' and the said output data signal D. That is, after the output OL of the NOR circuit 8 changes from 1 level to 0 level, since the output OH of the NAND circuit 7 changes from 1 level to 0 level, the simultaneous conducting state of a PMOSTQP and an NMOSTQN is eliminated and the through-current It does not almost flow. |
