Address translation buffer

摘要

An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.