| 摘要 |
PURPOSE:To vary optionally an execution speed without inflicting adverse influence upon a program by providing a pulse generator, which generates a holding signal which sets a computer to the holding state, and a variable resistor which varies the pulse width of the holding signal. CONSTITUTION:When a CPU1 enters into an OP code fetch cycle M1, a monostable multivibrator 2 starts the operation by an inverted M1 signal and an inverted MREQ signal. A pulse signal is outputted from an inverted 1Q terminal for a preliminarily set period and is inputted to the CPU1 as an inverted WAIT signal. The execution speed of the program is dependent upon the number of waits of the cycle M1. When this circuit is used, the number of waits of the cycle M1 is determined by the pulse width of the output signal from the inverted 1Q terminal of the monostable multivibrator 2. Consequently, the pulse width of the output signal is controlled by a variable resistor 8 to control optionally the program execution speed.
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