| 摘要 |
PURPOSE:To omit a complex competition circuit or a highly accurate refresh timer and to simplify the constitution of a device by actuating a refresh counter at the erasing time of an output from a pulse generator. CONSTITUTION:A dynamic RAM10 is refreshed by sending addresses to all memory cells once within a prescribed period. When a bus request confirmation signal (d) is supplied to a DMA controller 3 under control by a CPU1 and the operation of the DMA is started, the sending of a refresh signal is stopped, the output (g) of a monostable multivibrator 21 is turned to ''H'' level and the output (l) of an FF31 is turned to ''H'' level at the timing next to a clock (a), so that the refresh counter 22 is cleared. When the signal (d) is turned to ''L'' level, the DMA operation is stopped, the output of the counter 22 is held in a buffer 23 against an address bus 12 and the counter 22 counts up the clock (a). When the counter 22 outputs refresh addresses to all cells of the RAM10, a carry signal (j) is sent, the output (g) of the multivibrator 21 is turned to ''L'' level and the DMA operation is restarted. |
