发明名称 LOGIC ANALYZER
摘要 PURPOSE:To obtain displayed information accurately in time series and shorten a logic analysis time by providing a setter capable of setting and inputting a display area and displaying only the display area designated with the setter by a different system from other display areas. CONSTITUTION:Address information obtained through an input circuit 1 is sampled successively and stored in memory 2. The stored address data is read out by a control circuit 3 in the storage order, sent to a display device 4 after necessary processing for mapping display is carried out, and mapped and displayed on a display screen. Simultaneously, the circuit 3 outputs data from the starting point of the sample memory to a point designated with the setter 5 with different high brightness from other data, and their values are received from the setter 5 through an interface 6. Thus, only; the display area designated with the setter 5 is displayed with the different high brightness from other display areas. The displayed information is therefore traced easily in time series and the logic analysis time is shortened.
申请公布号 JPS60162961(A) 申请公布日期 1985.08.24
申请号 JP19840018872 申请日期 1984.02.03
申请人 YOKOKAWA HOKUSHIN DENKI KK 发明人 SAKURAI KAZUAKI
分类号 G01R13/28;G01R13/20;G06F11/22 主分类号 G01R13/28
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