| 摘要 |
PURPOSE:To attain ease of the processing in byte unit by converting a data word of 1-bit into a code word of 2-bit to allow the system to be adaptable even with self-clock. CONSTITUTION:A binary digital data incoming to an input terminal 1 is fed to an 8-bit shift register 6 and shifted sequentially in synchronizing with a pulse obtained from a clock signal from an input terminal device 3 through a 1/2 frequency divider 4. Then the original data in the register 6 is fed to a PAL (programmable array logic) 5, the arithmetic processing is conducted based on logical Equations I and II together with 3-bit past data M-3, M-2, M-1 from a shift register 7 to apply the 1-2 conversion. Then D-3, D-2, D-1, D0, D1, D2, D3, D4 are 8-bit data to a shift register 2 inputted in parallel with the PAL5 and D-3, D-2, D-1 are bit data in preceding over the 1-bit data D0 timewise. |
