发明名称 SPEED DETECTOR
摘要 PURPOSE:To improve precision in both a low-speed and a high-speed range by performing prescribed arithmetics while making low-speed clock pulses in the low-speed range or high-speed clock pulses in the high-speed range to correspond to pulses to be detected. CONSTITUTION:Pulses P to be detected which has a frequency proportional to a speed and is inputted from a circuit S1 are inputted to an input circuit 5, and the low-speed and high-speed clock pulses CLK1 and CLK2 are also inputted through circuits S2 and S3. A counter 7 receives an indication from a selection control circuit 9 to counts the number of detected pulses P of the low-speed clock pulses CLK1 in the low-speed range and the number of the high-speed clock pulses CLK2 in the high-speed range. The selection control circuit 9 knows the current speed from the counter 7 through circuits S11 and S6 to allow an input circuit to selects the clock pulses CLK1 or CLK2, and also output the selection state to respective control parts as a state signal.
申请公布号 JPS60159657(A) 申请公布日期 1985.08.21
申请号 JP19840014302 申请日期 1984.01.31
申请人 AMADA:KK 发明人 YOSHIOKA TERUHIKO
分类号 G01P3/489 主分类号 G01P3/489
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