Control circuit for autonomous counters of a plurality of CPU's or MPU's

摘要

In a control circuit for autonomous counters (41,42) acting as watchdog timers for a constantly operating first CPU (11) and intermittently operating second CPU (12) capable of transmitting data to and receiving data from each other, the first and the second CPU's respectively output first and second reset pulses (53) within prescribed intervals if operating normally. The first counter (41) is reset by the first reset pulses. The second counter (42) is reset by the second reset pulses when CPU (12) is operating and by the first reset pulses when it is not. The output of either the first or the second counter (on time out) is used to reset both CPU's. In a modification (Fig. 6) the counters are reset by the pulses (53) from their respective CPU's, but only the output of the first counter (41) is effective when the second CPU is not operating.