| 摘要 |
PURPOSE:To execute an instruction counter trace and an event trace of only a necessary part by providing a trace control memory which has stored trace information for showing whether a trace is necessary or not, and setting suitably the contents of trace control information. CONSTITUTION:A trace control memory 5 of a trace device 10 receives an address signal from an address bus 9A of a common bus 9. On the other hand, a trace control device 6 receives a control signal from a control bus 9C of the common bus 9. When a prescribed control signal is received, a processor 1 detects a fact that an access of some device or a memory has been started, and in this case, trace control information is read out of the trace control memory 5. Subsequently, in accordance with this trace control information, prescribed information loaded on the common bus 9 is fetched, and control for storing it in a trace information memory 7 is executed. |
