发明名称 CLOCK RECEPTION CIRCUIT
摘要 <p>PURPOSE:To attain normal clock switching operation without arrangement of the active system and the spare system by providing a circuit correcting the phase difference of a spare clock to an active clock so as to absorb the mutual phase difference between the clocks generated because of the difference of cable length. CONSTITUTION:The address is decided in advance so that a tap selection circuit 7 selects the spare clock in phase to the active clock among n-kind of the spare clocks having different delay amount at a delay circuit 6. Thus, the spare clock entering the delay circuit 6 via a level conversion circuit 2 is subject to the n- kind of delay times by the delay circuit 6, transmitted to the tap selection circuit 7 respectively, the clock in phase to the active clock is selected by the selection circuit 7 and transmitted to the selection circuit 4. The selection circuit 4 transmits the spare clock detected by the phase difference before the active clock is interrupted to a tank circuit 5. Since the spare clock with almost no phase difference is applied to the tank circuit 5 in place of the active clock, continuous clocks are transmitted from an output terminal.</p>
申请公布号 JPS60160237(A) 申请公布日期 1985.08.21
申请号 JP19840015638 申请日期 1984.01.31
申请人 FUJITSU KK 发明人 IKEDA TOSHIO;FUJII YUUZOU;IDEGUCHI HIROTOMO
分类号 H04B1/74;H04L7/00 主分类号 H04B1/74
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