发明名称 Multiplying circuit.
摘要 <p>In a muliplying operation, a first partial product corresponding to even times of the multiplicand can be produced by a shifting operation, while a second partial product corresponding to odd times of the multiplicand is produced by a shifting operation and an adding operation. In the described multiplying circuit, the first partial product is produced according to the result of a decoding operation for generating signals designating the partial product to be used in the multiplying operation. On the other hand the second partial product is independently produced regardless of the decoding result when the multiplicand is received to the multiplying circuit. Thus, a high speed multiplying operation can be achieved. </p>
申请公布号 EP0152046(A2) 申请公布日期 1985.08.21
申请号 EP19850101133 申请日期 1985.02.04
申请人 NEC CORPORATION 发明人 NUKIYAMA, TOMOJI
分类号 G06F7/533;G06F7/507;G06F7/508;G06F7/52;G06F7/53;(IPC1-7):G06F7/52 主分类号 G06F7/533
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