| 摘要 |
PURPOSE:To obtain linear phase adjustment with no step and to decrease the scale of circuit by using a CMOS gate circuit as a means to set the phase of a sampling pulse. CONSTITUTION:When a power voltage of the CMOS gate circuit 32 is adjusted by an output voltage of a time constant circuit 34, the relation of the phase between a comparison signal (SP2) and a clock run-in signal (CRI) is controlled to a prescribed relation to make the charge/discharge period to a capacitor 35 equal to each other. A sampling pulse with optimum phase to data is attained by controlling the phase of a sampling pulse (SP) in this way. |
