发明名称 HIGH SPEED SETTLING AMPLIFIER CIRCUIT
摘要 PURPOSE:To obtain a high speed settling amplifier circuit with high accuracy and high speed settling characteristic by feeding back an output of the post-stage of two amplifiers connected in cascade to an input of the prestage by means of a low dielectric absorption capacitor. CONSTITUTION:This high speed settling amplifier circuit has a sufficient amplification factor by overlapping the amplification factor of an error amplifier stage V1 onto the amplification factor of an auxiliary amplifier stage V2 and also and processing is applied by a feedback capacitor CF. As a result, the width of change in an output voltage is very small over all the operating range of the error amplifier stage V1 and the output current of the error amplifier stage V1 is not required basically, then the change in the input characteristic due to internal power consumption change is suppressed to a very small value. Since the response characteristic of the entire system depends on the feedback capacitor CF in this case, the settling time is decreased remarkably in comparison with a conventional circuit by using the low dielectric absorption and high insulation capacitor.
申请公布号 JPS60160210(A) 申请公布日期 1985.08.21
申请号 JP19840015384 申请日期 1984.01.31
申请人 YOKOGAWA HIYUURETSUTO PATSUKAADO KK 发明人 TAKAGI SHIYUN
分类号 H03F3/68 主分类号 H03F3/68
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