发明名称 INTEGRATION TEST CIRCUIT
摘要 PURPOSE:To make a DC check easily with a small number of test pins by providing a logical setting circuit in front of the final-stage output buffer circuit of an LSI, and using input pins as pseudo test pins. CONSTITUTION:The output of a gate circuit 21 which supplies a final output to a pin 26 of the LSI is supplied to the pin 26 through NAND circuits 22 and 23 constituting the test circuit and a buffer circuit 25. When the DC check is made, a test pin B and an input pin A1 are set at a level L, and an input pin A2 is switched to a level L or H; the output of the buffer circuit 25 is then switched to the level L or H forcibly to make the DC level check. When an action check is made, on the other hand, the test pin B is set to the level H, and then input signals from the input pins A1 and A2 become irrelevant to a forcible operating circuit 24, so that a pattern signal is inputted even from the input pins A1 and A2.
申请公布号 JPS60159664(A) 申请公布日期 1985.08.21
申请号 JP19840014285 申请日期 1984.01.31
申请人 TOSHIBA KK 发明人 TOKUMITSU SHIGENORI
分类号 G01R31/28;G01R31/317 主分类号 G01R31/28
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