| 摘要 |
PURPOSE:To realize a programmable frequency divider with less number of elements by frequency-dividing programmably plural clocks to use a count means in time division in common. CONSTITUTION:An M-stage counter 4 outputs a pulse at each count of 2M of an input clock and the pulse sets a flag 12. An output of L-set plugs 12 is connected to an input of a multiplexer 18, an output of the L-set plugs 12 is transmitted to an output of the multiplexer 18 and latched by a WRA signal at a latch 15 by the timing pulses of RD1-RDL. One of L-set data contenrs stored in a RAM17 read by a RAM read signal of the RD1-RDL is latched by an adder 16 by a WRA write signal and the signal latched by a latch 15 and the signal read by the RAM17 and latched to the adder 16 are added, and the result is outputted to a bus 20 in the timing of RDA.
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