发明名称 DECIMAL ARITHMETIC UNIT OF BIT SLICE SYSTEM
摘要 PURPOSE:To execute an operation of an undefined length operand, and also to execute a carry output from the most significant digit and a zero-detection of an significant digit by using a bit slice adder and subtracter. CONSTITUTION:The least significant digit of data to be operated A, B is allowed to be positioned in any digit, in an input of a decimal eight digit adder and subtracter 20. However, when the least significant digit of the data A, B is not positioned in the lowest digit of the input, it is required that the lower digit than the least significant digit is set to ''0''. Also, carry outputs CO0-CO7 from a decimal one digit adder and subtracter in the adder and subtracter 20 are supplied to a selector 40, and one of CO0-CO7 is selected and outputted as a carry output CO in accordance with the most significant digit position information EMSDP. An operation result Y is supplied to a digit zero detecting circuit 51, and a zero detection of each digit Y0-Y7 of the operation result Y is executed by an OR gate in the detecting circuit 51.
申请公布号 JPS60159937(A) 申请公布日期 1985.08.21
申请号 JP19840014708 申请日期 1984.01.30
申请人 TOSHIBA KK 发明人 ISHIKAWA TEI;EGUCHI KAZUTOSHI
分类号 G06F7/38;G06F7/00;G06F7/494;G06F7/50;G06F7/76 主分类号 G06F7/38
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