| 摘要 |
<p>PURPOSE:To secure assured synchronization even with an asynchronous signal and at the same time to reduce the variance of the synchronizing time, by sampling the FFs of the first train of a matrix circuit with a shift equivalent to a clock. CONSTITUTION:The high-speed clocks TCLK having cycles shorter than the settling time are supplied to all FFs as well as to N FF(T). Then gate pulses T1- Tn having shifted phases are supplied successively and repetitively to all AND gates of each row. The AND logics are obtained at the AND gates of the first train with the asynchronous output given from an FF(R). Then this output is supplied to the FFs of the first train. The input signals are sampled successively at the FF with the timing of the clock TCLK and with (n) units of clocks which are shifted substantially by a clock. As these clocks have high-speed operations, at least an FF of the first train is set assuredly and then the subsequent FFs are set. Then the output of the FF of the final train is supplied to the FF(T), and this FF(T) is set. The same delay time is obtained when viewed from the FF(T) and therefore the variance of the synchronizing time can be reduced.</p> |
