发明名称 MEMORY ACCESS CONTROL SYSTEM
摘要 PURPOSE:To simplify memory control by providing a means, which counts data when data written in an FIFO memory is read out, and a setting means of a prescribed value and permitting read when the counted value of data coincides with the prescribed value. CONSTITUTION:In case of write, counters 5 and 6 are driven by write clocks WCL, and the counter 6 counts data each time when data is written in a memory 2. When data is read out, a processor 4 sets preliminarily a numerical value l, which designates the number of data, to a register 7. In case of write of data, when the value of an output L of the counter 6 coincides with the numberical value l, a discriminating part 8 transmits an output signal C to the processor 4, and a control part 9 generates a control signal G by a start signal ST to start a reading part 3 and outputs read clocks RCL from a signal generating part 10. Consequently, a counter 11 is driven to read data in the momory 2.
申请公布号 JPS60157793(A) 申请公布日期 1985.08.19
申请号 JP19840012728 申请日期 1984.01.26
申请人 FUJI FUAKOMU SEIGIYO KK;FUJITSU KK 发明人 OGURA YOSHINORI;IGATA KEIICHIROU
分类号 G11C7/00;(IPC1-7):G11C7/00 主分类号 G11C7/00
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