| 摘要 |
PURPOSE:To reduce a phase delay and to omit a phase compensating circuit, etc., by detecting a speed error not by the phase comparison but the detection of frequency difference. CONSTITUTION:The n-bit binary counters start simultaneously counting the extracted clock frequency fc and the reference clock frequency fr which are proportional to the revolving speed of a spindle or a disk. An equation I shows the average voltage Ve of an error output showing a time difference obtained between both counters when they finish their counting. The outputs Qn and Qn' of counters C1 and C2 are shown in figures (a) and (b) respectively. While a figure (c) shows the output voltage Ve. The amplitude and the pulse width W of the voltage Ve are set Vo and 2<n>(1/fc-1/fr) respectively. The cycle of the output Q'n+1 of the counter C2 is double as much as that of the output Qn'. The mean value of the Ve within a period 2<n>/frX2 shown by an equation II, i.e., an equation I . A circuit shown in the figure serves as a phase comparator 24 followed by an LPF26 at the next stage. The LPF26 averages the Ve. In such a constitution, a phase compensating circuit 28 can be omitted and the output of the LPF26 is supplied to a driver 14. |
