| 摘要 |
PURPOSE:To attain signal processing by dividing an adder ratio comparison and selection circuit into an addition/comparion unit and an addition/selection unit and providing a loop from which remaining path length is fed back not through a subtraction circuit. CONSTITUTION:A remaining path length GAMMA' is outputted from a selector 22 at a time 3T after a path length lambda1 is outputted from a lambda register 2. Since the remaining path length GAMMA' is fed to an adder 19b through a GAMMA' register 4b, a one-cycle signal processing is completed by a time of 4T only. Since the remaining path length GAMMA' outputted from the selector 22 in the addition/selection unit is fed back to the addition/comparison unit 6b without subtraction processing, the high speed signal processing is attained.
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