| 摘要 |
<p>An analogue voltage-to-digital voltage converter has a voltage divider with a plurality of stages each providing an output voltage for comparison with the unknown voltage and in addition provides interpolation between the output voltage to improve the accuracy. Interpolation is effected by adding a ramp voltage to the unknown ramping through a magnitude equivalent to the voltage of at least one stage. With one tap on the voltage divider selected, comparison of the unknown plus ramp voltage is effected successively as the voltage ramps. By noting when the combined voltage reaches the level of one of the divider output voltages and by counting the number of comparisons made from the time when the ramp voltage is at a predetermined magnitude and comparing this with the time taken to ramp through one or a plurality of whole divider stages, determination can be made of the magnitude of the unknown voltage to a fraction of a stage.</p> |
