| 摘要 |
PURPOSE:To compensate the absence of a desired number of bit timing components, by adding a phase information holding circuit which has prescribed holding characteristics to PLL. CONSTITUTION:Differentiating circuit 1, on detecting each rise of a PCM signal input, samples and holds the output of integrator 3 and, at the same time, cancels the integral value of integrator 3, thereby newly starting integration. The output of sample holding circuit 4 is fed back to voltage-controlled oscillator 6 via loop filter 5, constituting PLL. |
