发明名称 ARITHMETIC LOGIC CIRCUIT
摘要 PURPOSE:To improve the speed of carry propagation from the lowest-order bit to the highest-order bit so as to improve the processing efficiency of the titled circuit, by newly providing a means for making discharge quicker at every bit on a carry propagating line. CONSTITUTION:During the period of a clock phi2, (n) channel type transistor (TR) 1a and 1b are turned on and points 1R and 1S are discharged and become low levels, and then, a point 1q is precharged to the electric potential which is one-step lower then the supply voltage. When carry is forwards from the previous step of the n-th step to inversion phi2 and inversion Cn-1=0, and then, the OR of the bits of the n-th step is '1' during the next calculating period, a transfer gate 1f is turned on and the carry from the previous step is propagat ed. If the potential at the point 1Q drops a little, the potential at a point 1V becomes one which is one-step lower then the potential at the point 1Q by means of a TR1m and, when the potential at the point 1V becomes lower than the input level of a TR1n, the TR1n and another TR1p are turned on. As a result, the potential at the point 1Q rapidly drops by means of positive feedback action.
申请公布号 JPS61168041(A) 申请公布日期 1986.07.29
申请号 JP19850009440 申请日期 1985.01.22
申请人 NEC CORP 发明人 NAKAMURA TAKAYOSHI
分类号 G06F7/50;G06F7/503;G06F7/508 主分类号 G06F7/50
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