发明名称 Circuit arrangement for inputting an analog voltage value at zero potential into a digital evaluating circuit
摘要 A circuit arrangement is specified which enables an analog voltage value to be input at zero potential into a digital evaluating circuit with the least possible complexity. For this purpose, an A/D converter circuit operating in accordance with the dual-slope method and exhibiting an integration section and a control section is used. The potential isolating circuit means (relay, optocoupler) are then arranged in such a manner that the potential is isolated between integration section and control section. Since there are only three DC connections between the two circuit sections at this point, the expenditure of potential-isolating circuit means is much lower than when the potential is isolated at the digital output of the A/D converter circuit. <IMAGE>
申请公布号 DE3404956(A1) 申请公布日期 1985.08.14
申请号 DE19843404956 申请日期 1984.02.11
申请人 STANDARD ELEKTRIK LORENZ AG 发明人 POSCHMANN,WERNER,DIPL.-ING.;HEISER,MICHAEL;ARNOLD,GERD,DIPL.-ING.
分类号 H03M1/00 主分类号 H03M1/00
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