MEASUREMENT TIMING GENERATING CIRCUIT

摘要

PURPOSE:To synchronize the time with a reference time by comparing a phase jitter with a frequency-division timing signal of the reference frequency and integrating the number of times of detection of the phase jitter when the jitter is larger than a prescribed value to control the phase of the frequency division timing signal when the integrated value exceeds a prescribed value. CONSTITUTION:The timing signal in synchronization with the reference time is fed to an input terminal 1 and a reference frequency signal is supplied to an input terminal 7. The reference frequency signal is fed to an AND circuit 9 and a down-counter 12 via a waveform shaping circuit 8. The counter 12 supplies a timing signal G of high stability to an output terminal 14 and an NOT output H to an AND circuit 11, respectively. A phase jitter DELTAT is outputted from an exclusive OR circuit 3 and the width is compared with a time width T of a prescribed phase jitter by a J-K flip-flop circuit 4 and a shift register 5. The number of times of generation of the phase jitter having the relation of DELTAT>T is integrated by a shift register 6 and when the integrated value reaches N times, an output signal E is fed to the OR circuit 11 and the output signal F matches the timing set by a setting circuit 13 to the timing corrected with the phase jitter.