| 摘要 |
<p>PURPOSE:To obtain a normal clock signal without disturbance in the duty cycle by locking an input of a frequency division circuit outputting a clock signal in synchronizing with the leading of the clock signal after the leading of a stop control signal. CONSTITUTION:A oscillation output signal OSC is outputted from an oscillation circuit 21 connected with a crystal vibrator 22 and the normal clock signal CLK is transmitted from a frequency division circuit 24 comprising flip-flops FFs 25, 26 and an NOR circuit 27 via an AND circuit 23. The stop control signal STBY is fed in parallel with the FFs 29, 30 as a synchronizing signal CP, and a Q output signal Q1 of the FF29 is fed to a data D input signal of the FF31 and a Q' output signal Q'2 of the FF31 is fed to one input terminal of the AND circuit 23. A Q output signal Q3 of the FF30 is transmitted by the trailing of the stop control signal, fed to a clear terminal of the FFs 25, 26 of a frequency division circuit 24 and the state is brought into the initial state.</p> |
