| 摘要 |
PURPOSE:To reduce the area of a memory cell by forming one part of a transfer gate section and a bit line on an isolation region. CONSTITUTION:A region 9a as one part of a transfer gate region 9 in a memory cell and a bit line 7 are positioned in an isolation region 2 between elements constituting the memory cell shaped to a substrate 1. That is, an epitaxial growth region 12 grown in the lateral direction along the region 2 up to one part of the upper side of the region 2 from an active region 3 in the P type substrate 1 between a storage gate 8 and the region 2 is formed, and an end section region on the region 2 in the region 12 is used as the bit line 7. A region 8a up to the bit line 7 from the region 3 is used as one part of the region 9. Consequently, there is no isolation region between the bit line 7 and a storage gate region in an adjacent memory cell. Accordingly, an occupying area on a chip can be reduced. |
